Display substrate and display device

ABSTRACT

A display substrate includes a base substrate including a display area and a peripheral area located at least on a first side of the display area. A plurality of pixel units are arranged in the display area. A first power trace is located in the peripheral area. A scan driving circuit is located in the peripheral area. The scan driving circuit includes a first scan driving circuit and a second scan driving circuit. A layer where the first power trace is located is located on a side of a layer where the scan driving circuit is located away from the base substrate. An orthographic projection of the first power trace on the base substrate at least partially overlaps an orthographic projection of the first scan driving circuit on the base substrate, and at least partially overlaps an orthographic projection of the second scan driving circuit on the base substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Chinese Patent Application No.202110323225.0 filed on Mar. 25, 2021 in the State Intellectual PropertyOffice of China, the whole disclosure of which is incorporated herein byreference.

TECHNICAL FIELD

The present disclosure relates to a field of a display technology, andin particular to a display substrate and a display device.

BACKGROUND

With a development of an electronic technology, display devices such assmart phones are used more and more frequently in users' lives, andbecome more and more important to users. A large-screen mobile phone mayhave a large display area, which is more in line with users' needs ofbrowsing web pages, reading books, watching movies, playing games, andso on. Therefore, a frame of a current display device is gettingnarrower and narrower, so as to increase a screen-to-body ratio andimprove user experience.

The above information disclosed in this section is only for theunderstanding of the background of a technical concept of the presentdisclosure. Therefore, the above information may contain informationthat does not constitute a related art.

SUMMARY

In an aspect, there is provided a display substrate, including: a basesubstrate including a display area and a peripheral area located atleast on a first side of the display area; a plurality of pixel unitsarranged in the display area of the base substrate, wherein the pixelunit includes a pixel driving circuit and a light emitting deviceelectrically connected to the pixel driving circuit, and the lightemitting device includes a first electrode; a first power trace locatedin the peripheral area and electrically connected to the firstelectrode; and a scan driving circuit arranged on the base substrate andlocated in the peripheral area, wherein the scan driving circuitincludes a first scan driving circuit for generating a first scan signaland a second scan driving circuit for generating a second scan signal,wherein a layer where the first power trace is located is located on aside of a layer where the scan driving circuit is located away from thebase substrate; and an orthographic projection of the first power traceon the base substrate at least partially overlaps an orthographicprojection of the first scan driving circuit on the base substrate, andthe orthographic projection of the first power trace on the basesubstrate at least partially overlaps an orthographic projection of thesecond scan driving circuit on the base substrate.

According to some exemplary embodiments, the second scan driving circuitis located on a side of the first scan driving circuit away from thedisplay area, and the orthographic projection of the first power traceon the base substrate covers the orthographic projection of the secondscan driving circuit on the base substrate.

According to some exemplary embodiments, a width of an overlappingportion of the orthographic projection of the first power trace on thebase substrate and the orthographic projection of the first scan drivingcircuit on the base substrate in a first direction is more than 40% of awidth of the first scan driving circuit in the first direction, whereinthe first direction is a direction from the display area to theperipheral area.

According to some exemplary embodiments, the first scan driving circuitis spaced apart from the second scan driving circuit, and theorthographic projection of the first power trace on the base substratecovers an orthographic projection of a gap between the first scandriving circuit and the second scan driving circuit on the basesubstrate.

According to some exemplary embodiments, the first scan driving circuitis spaced apart from the second scan driving circuit; the first powertrace includes a first sub-trace and a second sub-trace, and the firstsub-trace is spaced apart from the second sub-trace; and a gap betweenthe first sub-trace and the second sub-trace exposes a gap between thefirst scan driving circuit and the second scan driving circuit.

According to some exemplary embodiments, the display substrate furtherincludes a conductive connecting portion located at least partiallybetween the layer where the first power trace is located and a layerwhere the first electrode is located, so as to electrically connect thefirst power trace and the first electrode.

According to some exemplary embodiments, an orthographic projection ofthe conductive connecting portion on the base substrate at leastpartially overlaps the orthographic projection of the first scan drivingcircuit on the base substrate, and the orthographic projection of theconductive connecting portion on the base substrate covers theorthographic projection of the second scan driving circuit on the basesubstrate.

According to some exemplary embodiments, the conductive connectingportion is in contact with the first power trace, and a width of aportion of the first power trace in contact with the conductiveconnecting portion in the first direction is more than 50% of a width ofthe first power trace in the first direction, wherein the firstdirection is a direction from the display area to the peripheral area.

According to some exemplary embodiments, the display substrate furtherincludes a first barrier component arranged on a side of the first powertrace away from the base substrate, wherein an orthographic projectionof the first barrier component on the base substrate at least partiallyoverlaps the orthographic projection of the second scan driving circuiton the base substrate.

According to some exemplary embodiments, the second scan driving circuitincludes an edge portion away from the display area, and theorthographic projection of the first barrier component on the basesubstrate is located on a side of an orthographic projection of the edgeportion on the base substrate close to the display area.

According to some exemplary embodiments, the display substrate furtherincludes a second barrier component arranged on a side of the firstpower trace away from the base substrate, wherein the second barriercomponent is located on a side of the first barrier component away fromthe display area; and an orthographic projection of the second barriercomponent on the base substrate at least partially overlaps anorthographic projection of the edge portion of the second scan drivingcircuit on the base substrate.

According to some exemplary embodiments, the display substrate furtherincludes a conductive trace located in the peripheral area, wherein theconductive trace is located on a side of the second scan driving circuitaway from the display area and is located on a side of the first powertrace close to the base substrate, and the conductive trace iselectrically connected to the first power trace.

According to some exemplary embodiments, the light emitting devicefurther includes a second electrode and a light emitting layer arrangedbetween the first electrode and the second electrode, the scan drivingcircuit includes at least one thin film transistor arranged on the basesubstrate, and the thin film transistor includes an active layer, a gateelectrode, a source electrode and a drain electrode; and wherein thedisplay substrate further includes: a first conductive layer arranged ona side of the active layer away from the base substrate, wherein thegate electrode is located in the first conductive layer; a secondconductive layer arranged on a side of the first conductive layer awayfrom the base substrate, wherein the source electrode and the drainelectrode are located in the second conductive layer; and a thirdconductive layer arranged on a side of the second conductive layer awayfrom the base substrate, wherein at least a portion of the second powertrace is located in the second conductive layer and/or the thirdconductive layer.

According to some exemplary embodiments, the first electrode is acathode electrode of an organic light emitting device, and the secondelectrode is an anode electrode of the organic light emitting device.

In another aspect, there is provided a display device including thedisplay substrate described above.

BRIEF DESCRIPTION OF THE DRAWINGS

By describing in detail exemplary embodiments of the present disclosurewith reference to the drawings, the features and advantages of thepresent disclosure will become more apparent.

FIG. 1 shows a plan view of a display substrate according to someexemplary embodiments of the present disclosure.

FIG. 2 shows a partial plan view of the display substrate according tosome exemplary embodiments of the present disclosure at part I in FIG.1.

FIG. 3 shows a cross-sectional view of the display substrate accordingto some exemplary embodiments of the present disclosure taken along lineAA′ in FIG. 2.

FIG. 4 shows a cross-sectional view of the display substrate accordingto other exemplary embodiments of the present disclosure taken alongline AA′ in FIG. 2.

FIG. 5 shows a cross-sectional view of the display substrate accordingto some exemplary embodiments of the present disclosure taken along lineBB′ in FIG. 1.

FIG. 6 shows a circuit diagram of a gate scanning shift register unitincluded in a first scan driving circuit according to some exemplaryembodiments of the present disclosure.

FIG. 7 shows a schematic diagram of a layout of the gate scanning shiftregister unit included in the first scan driving circuit on the basesubstrate according to some exemplary embodiments of the presentdisclosure.

FIG. 8 shows a circuit diagram of a light emission control scanningshift register unit included in a second scan driving circuit accordingto some exemplary embodiments of the present disclosure.

FIG. 9 shows a schematic diagram of a layout of the light emissioncontrol scanning shift register unit included in the second scan drivingcircuit on the base substrate according to some exemplary embodiments ofthe present disclosure.

FIG. 10 shows a schematic diagram of a display device according to someexemplary embodiments of the present disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

In order to make the objectives, technical solutions and advantages ofthe present disclosure more apparent, the technical solutions of theembodiments of the present disclosure are clearly and completelydescribed below with reference to the drawings. Obviously, the describedembodiments are only a part but not all of the embodiments of thepresent disclosure. Based on the embodiments of the present disclosure,all other embodiments obtained by those ordinary skilled in the artwithout carrying out inventive effort fall within the protection scopeof the present disclosure.

It should be noted that, in the drawings, for clarity and/or descriptionpurposes, size and relative size of elements may be enlarged.Accordingly, the size and relative size of each element need not to belimited to those shown in the drawings. In the specification anddrawings, the same or similar reference numerals indicate the same orsimilar components.

When an element is described as being “on”, “connected to” or “coupledto” another element, the element may be directly on the other element,directly connected to the other element, or directly coupled to theother element, or an intermediate element may be present. However, whenan element is described as being “directly on”, “directly connected to”or “directly coupled to” another element, no intermediate element isprovided. Other terms and/or expressions used to describe therelationship between elements, for example, “between” and “directlybetween”, “adjacent” and “directly adjacent”, “on” and “directly on”,and so on, should be interpreted in a similar manner. In addition, theterm “connected” may refer to a physical connection, an electricalconnection, a communication connection, and/or a fluid connection. Inaddition, X-axis, Y-axis and Z-axis are not limited to three axes of arectangular coordinate system, and may be interpreted in a broadermeaning. For example, the X-axis, the Y-axis and the Z-axis may beperpendicular to each other, or may represent different directions thatare not perpendicular to each other. For the objective of the presentdisclosure, “at least one of X, Y and Z” and “at least one selected froma group consisting of X, Y and Z” may be interpreted as only X, only Y,only Z, or any combination of two or more of X, Y and Z, such as XYZ,XYY, YZ and ZZ. As used herein, the term “and/or” includes any and allcombinations of one or more of the listed related items.

It should be noted that although the terms “first”, “second”, and so onmay be used herein to describe various components, members, elements,regions, layers and/or parts, these components, members, elements,regions, layers and/or parts should not be limited by these terms.Rather, these terms are used to distinguish one component, member,element, region, layer and/or part from another. Thus, for example, afirst component, a first member, a first element, a first region, afirst layer and/or a first part discussed below may be referred to as asecond component, a second member, a second element, a second region, asecond layer and/or a second part without departing from the teachingsof the present disclosure.

For ease of description, spatial relationship terms, such as “upper”,“lower”, “left”, “right”, may be used herein to describe therelationship between one element or feature and another element orfeature as shown in the figure. It should be understood that the spatialrelationship terms are intended to cover other different orientations ofthe device in use or operation in addition to the orientation describedin the figure. For example, if the device in the figure is turned upsidedown, an element or feature described as “below” or “under” anotherelement or feature will be oriented “above” or “on” the other element orfeature.

Those skilled in the art should understand that in the presentdisclosure, unless otherwise specified, the expression “height” or“thickness” refers to a size in a direction perpendicular to a surfaceof each film layer arranged in the display substrate, that is, a size inthe light emitting direction of the display substrate, or called a sizein a normal direction of the display device.

In the present disclosure, unless otherwise specified, the expression“patterning process” generally includes steps of photoresist coating,exposure, development, etching, and photoresist stripping. Theexpression “one-time patterning process” means a process of formingpatterned layers, components, members and so on by using one mask.

It should be noted that the expressions “same layer”, “arranged in thesame layer” or similar expressions refer to a layer structure formed byusing the same film forming process to form a film layer for forming aspecific pattern, and then using the same mask to pattern the film layerby using one-time patterning process. Depending on the specificpatterns, the one-time patterning process may include multiple exposure,development or etching processes, and the specific pattern in the layerstructure formed may be continuous or discontinuous. These specificpatterns may also be at different heights or have different thicknesses.

In the present disclosure, unless otherwise specified, the expression“electrically connected” may mean that two components or elements aredirectly electrically connected. For example, component or element A isin direct contact with component or element B, and electrical signalsmay be transmitted between the two components or elements. It may alsomean that two components or elements are electrically connected througha conductive medium such as a conductive wire. For example, component orelement A is electrically connected to component or element B through aconductive wire so as to transmit electrical signals between the twocomponents or elements. Alternatively, it may also mean that twocomponents or elements are electrically connected through at least oneelectronic component. For example, component or element A iselectrically connected to component or element B through at least onethin film transistor so as to transmit electrical signals between thetwo components or elements.

The embodiments of the present disclosure provide at least a displaysubstrate and a display device. The display substrate includes: a basesubstrate including a display area and a peripheral area located atleast on a first side of the display area; a plurality of pixel unitsarranged in the display area of the base substrate, wherein the pixelunit includes a pixel driving circuit and a light emitting deviceelectrically connected to the pixel driving circuit, and the lightemitting device includes a first electrode; a first power trace locatedin the peripheral area and electrically connected to the firstelectrode; a scan driving circuit arranged on the base substrate andlocated in the peripheral area, wherein the scan driving circuitincludes a first scan driving circuit for generating a first scan signaland a second scan driving circuit for generating a second scan signal,and a layer where the first power trace is located is located on a sideof a layer where the scan driving circuit is located away from the basesubstrate; and an orthographic projection of the first power trace onthe base substrate at least partially overlaps an orthographicprojection of the first scan driving circuit on the base substrate, andthe orthographic projection of the first power trace on the basesubstrate at least partially overlaps an orthographic projection of thesecond scan driving circuit on the base substrate. In the embodiments ofthe present disclosure, in the peripheral area, the first power traceand the scan driving circuit are stacked, which is beneficial to achievea display device with a narrow frame.

FIG. 1 shows a plan view of a display substrate according to someexemplary embodiments of the present disclosure. FIG. 2 shows a partialplan view of the display substrate according to some exemplaryembodiments of the present disclosure at part I in FIG. 1. FIG. 3 showsa cross-sectional view of the display substrate according to someexemplary embodiments of the present disclosure taken along line AA′ inFIG. 2. FIG. 4 shows a cross-sectional view of the display substrateaccording to other exemplary embodiments of the present disclosure takenalong line AA′ in FIG. 2. FIG. 5 shows a cross-sectional view of thedisplay substrate according to some exemplary embodiments of the presentdisclosure taken along line BB′ in FIG. 1. Referring to FIG. 1 to FIG.5, the display substrate 1 may include a base substrate 10. For example,the base substrate 10 may be formed of glass, plastic, polyimide, orother materials. The base substrate 10 includes a display area AA and aperipheral area (or referred to as a non-display area) NA located on atleast one side of the display area AA.

Referring to FIG. 1, the display substrate 1 may include a plurality ofpixel units P (schematically shown by a dashed box in FIG. 1) arrangedin the display area AA. The plurality of pixel units P may be arrangedin an array in a first direction X and a second direction Y on the basesubstrate 10. Each of the pixel units P may further include a pluralityof sub-pixels, such as a red sub-pixel, a green sub-pixel and a bluesub-pixel. A sub-pixel SP is schematically shown in FIG. 1.

For example, the display substrate may include a signal input side IN1(a lower side shown in FIG. 1). A data driving chip IC may be providedon the signal input side IN1. The data driving chip IC may beelectrically connected to the pixel unit P located in the display areathrough a plurality of signal traces, and the pixel driving circuit maybe electrically connected to the data driving chip IC. In this way, asignal such as a data signal may be transmitted from the signal inputside IN1 to the plurality of pixel units P.

For example, as shown in FIG. 1, the peripheral area NA may be locatedon four sides of the display area AA, that is, the peripheral area NAsurrounds the display area AA.

It should be noted that in the drawings, the pixel unit and thesub-pixel are schematically shown in a rectangular shape, but this doesnot constitute a limitation on the shape of the pixel unit and thesub-pixel included in the display substrate provided by the embodimentsof the present disclosure.

Exemplarily, the display substrate 1 may include a scan driving circuitarranged on the base substrate 10 and located in the peripheral area NA.For example, the scan driving circuit may include a plurality of scandriving shift register units connected in cascade.

Referring to FIG. 1, the scan driving circuit may include a first scandriving circuit 20 for generating a first scan signal and a second scandriving circuit 30 for generating a second scan signal. For example, thefirst scan signal may be a gate scanning signal, and the first scandriving circuit may be a gate scan driving circuit (Gate GOA); thesecond scan signal may be a light emission control scan signal, and thesecond scan driving circuit may be a light emission control scan drivingcircuit (EM GOA). Exemplarily, the first scan driving circuit 20 mayinclude a plurality of gate scanning shift register units 201 connectedin cascade for providing the plurality of pixel units P with, forexample, gate scanning signals shifted row by row. The second scandriving circuit 30 may include a plurality of light emission controlscanning shift register units 301 connected in cascade for providing theplurality of pixel units P with, for example, light emission controlsignals shifted row by row.

In a GOA technology, a gate driving circuit and a light emission controlscan driving circuit are directly arranged on the array substrate,instead of using an external driving chip. For example, each GOA unitmay act as a stage of shift register unit, and each stage of shiftregister unit may be electrically connected to a gate line or a lightemission control line. Each stage of shift register unit may output aturn-on voltage in turn, so as to achieve a progressive scanning of thepixel units. In some embodiments, each stage of shift register unit mayalso be connected to a plurality of gate lines or a plurality of lightemission control lines. This may adapt to a development trend of highresolution and narrow frame of a display panel.

In the embodiments of the present disclosure, each pixel unit P mayinclude a pixel driving circuit 40 and a light emitting device 50electrically connected to the pixel driving circuit. For example, thelight emitting device 50 may be an organic light emitting diode (OLED)or a quantum dot light emitting diode (QLED). Referring to FIG. 5, thelight emitting device 50 may include a first electrode 501, a secondelectrode 502, and a light emitting layer 503 arranged between the firstelectrode and the second electrode.

One of the first electrode 501 and the second electrode 502 is an anodeelectrode, and the other is a cathode electrode. For example, the firstelectrode 501 may be the cathode electrode, and the second electrode 502may be the anode electrode. The light emitting layer 503 may have amultilayer structure, for example, it may include a multilayer structureincluding a hole injection layer, a hole transport layer, an organiclight emitting layer, an electron transport layer and an electroninjection layer.

It should be noted that for example, an active drive or a passive drivemay be adopted for the light emitting device 50 of the organic lightemitting diode. A passive drive OLED array substrate includes a cathodeelectrode and an anode electrode, an intersection of the anode electrodeand the cathode electrode may emit light, and the driving circuit may beexternally mounted by a connecting method such as a tape carrier packageor a chip-on-glass. An active drive OLED array substrate may provideeach pixel with a pixel driving circuit. The pixel driving circuit mayinclude a thin film transistor with a switching function (that is, aswitching transistor), a thin film transistor with a driving function(that is, a driving transistor), and a charge storage capacitor. Inaddition, the pixel driving circuit may further include other types ofthin film transistor with a compensation function. It should beunderstood that, in the embodiments of the present disclosure, thedisplay substrate may be provided with various types of existing pixeldriving circuits, which will not be repeated here. For example, eachpixel unit P may include a pixel driving circuit having a circuitstructure of 7T1C, 7T2C, 8T2C or 4T1C. The pixel driving circuit mayoperate under the control of a data signal transmitted through the dataline and a gate scanning signal and a light emission control signaltransmitted through the signal line, so as to drive the light emittingdevice to emit light, and thus realize display and other operations.

For example, as shown in FIG. 5, the display substrate 1 may include adriving circuit layer. The pixel driving circuit described above may bearranged in the driving circuit layer. An insulating layer may beprovided between the driving circuit layer and the light emitting device50. The insulating layer may be a single insulating film layer or astacked layer including a plurality of insulating film layers.

For example, the display substrate 1 may further include various signallines arranged on the base substrate 10. The various signal lines mayinclude a data line, a gate scanning signal line, a light emissioncontrol signal line, a first power trace, a second power trace and soon, so as to provide various signals such as a data signal, a gatescanning signal, a light emission control signal, a first power supplyvoltage, a second power supply voltage and so on to the pixel drivingcircuit in each sub-pixel. In the embodiment shown in FIG. 1, a scanline GL and a data line DL are schematically shown. The scan line GL andthe data line DL may be electrically connected to each pixel unit P.

Referring to FIG. 3 to FIG. 5, the display substrate 1 may include: asemiconductor layer 2 arranged on the base substrate 10, a firstinsulating layer 31 arranged on a side of the semiconductor layer 2 awayfrom the base substrate 1, a first conductive layer 4 arranged on a sideof the first insulating layer 31 away from the base substrate 10, asecond insulating layer 32 arranged a side of the first conductive layer4 away from the base substrate 10, a second conductive layer 5 arrangedon a side of the second insulating layer 32 away from the base substrate10, a third insulating layer 33 arranged on a side of the secondconductive layer 5 away from the base substrate 10, a third conductivelayer 6 arranged on a side of the third insulating layer 33 away fromthe base substrate 10, a fourth insulating layer 34 arranged on a sideof the third conductive layer 6 away from the base substrate, a fourthconductive layer 7 arranged on a side of the fourth insulating layer 34away from the base substrate 10, a pixel defining layer PDL arranged ona side of the fourth conductive layer 7 away from the base substrate 10,a light emitting layer 503 arranged on a side of the pixel defininglayer PDL away from the base substrate 10, and a fifth conductive layer8 arranged on a side of the light emitting layer 503 away from the basesubstrate 10.

Optionally, a film layer 22 such as a buffer layer and a barrier layermay be further provided between the base substrate 10 and thesemiconductor layer 2.

For example, in the display area AA, the pixel driving circuit 40 mayinclude a plurality of thin film transistors, and each thin filmtransistor may include an active layer, a gate electrode, a sourceelectrode and a drain electrode. For example, FIG. 5 schematically showsa thin film transistor as well as an active layer, a gate electrode, asource electrode 5401 and a drain electrode D401 thereof. The activelayer of the thin film transistor of the pixel driving circuit 40 islocated in the semiconductor layer 2, the gate electrode is located inthe first conductive layer 4, and the source electrode 5401 and thedrain electrode D401 are located in the second conductive layer 5. Forexample, the drain electrode D401 may be electrically connected to thesecond electrode 502 through a conductive connecting portion located inthe third conductive layer 6.

For example, the first insulating layer 31 may include a gate insulatinglayer, the second insulating layer 32 may include an interlayerdielectric layer, the third insulating layer 33 may include apassivation layer and/or a first planarization layer, and the fourthinsulating layer 34 may include a second planarization layer. Foranother example, each of the first insulating layer 31, the secondinsulating layer 32, the third insulating layer 33 and the fourthinsulating layer 34 may include a single-layer film structure or astacked-layer film structure. The first insulating layer 31 and thesecond insulating layer 32 may contain an inorganic insulating material.The third insulating layer 33 and the fourth insulating layer 34 maycontain an inorganic insulating material, an organic insulatingmaterial, or any combination thereof. For example, the inorganicinsulating material may include silicon oxide, silicon nitride, siliconoxynitride, and the like. The organic insulating material may includepolyimide, polyamide, acrylic resin, phenol resin, benzocyclobutene, andthe like.

For example, the second electrode 502 may be located in the fourthconductive layer 7, and the first electrode 501 may be located in thefifth conductive layer 8.

In the display area AA, the pixel defining layer PDL may include anopening located in each sub-pixel. The opening may expose a portion ofthe second electrode 502. A portion of the light emitting layer 503fills the opening and is in contact with the exposed portion of thesecond electrode 502. The first electrode 501 is located on a side ofthe light emitting layer 503 away from the base substrate 10.

Exemplarily, the first conductive layer may be a conductive layer madeof a gate material, the second conductive layer and the third conductivelayer may be a conductive layer made of a source/drain material, thefourth conductive layer may be a conductive layer made of an anodematerial, and the fifth conductive layer may be a conductive layer madeof a cathode material.

For example, the gate material may include a metal material, such as Mo,Al, Cu and other metals and alloys thereof. The source/drain materialmay include a metal material, such as Mo, Al, Cu and other metals andalloys thereof, or Ti/Al/Ti and other materials. The anode material mayinclude a conductive metal material, such as magnesium, aluminum,lithium and other metals and alloys thereof, or indium tin oxide (ITO),indium zinc oxide (IZO), and the like. The cathode material may includea transparent conductive material, such as indium tin oxide (ITO),indium zinc oxide (IZO), and the like.

For example, the first power trace may be a trace for providing a VSSvoltage signal, and the second power trace may be a trace for providinga VDD voltage signal. For example, the first power trace is electricallyconnected to the first electrode 501, and the second power trace iselectrically connected to the second electrode 502. It should be notedthat “the second power trace is electrically connected to the secondelectrode” here may mean that the second power trace is electricallyconnected to the second electrode through an electronic component suchas the thin film transistor in the pixel driving circuit.

Referring to FIG. 2, FIG. 3 and FIG. 4, in the embodiments of thepresent disclosure, the scan driving circuit and the first power traceare both arranged in the peripheral area NA, and a stacked-layer designis adopted for the scan driving circuit and the power trace in theperipheral area. That is, an orthographic projection of the first powertrace on the base substrate at least partially overlaps an orthographicprojection of the scan driving circuit on the base substrate.Specifically, the first scan driving circuit 20, the second scan drivingcircuit 30 and the first power trace 60 are all arranged in theperipheral area NA. An orthographic projection of the first power trace60 on the base substrate 10 at least partially overlaps an orthographicprojection of the first scan driving circuit 20 on the base substrate10, and the orthographic projection of the first power trace 60 on thebase substrate 10 at least partially overlaps an orthographic projectionof the second scan driving circuit 30 on the base substrate 10. Throughthis stacked-layer design, a space of the peripheral area in a thicknessdirection of the display substrate may be fully utilized to arrange thefirst power trace, so as to reduce an occupation width of the firstpower trace in the peripheral area, which may reduce a width of a frameof the display substrate and facilitate the realization of a displaydevice with a narrow frame.

It should be noted that the first power trace 60 is used to transmit theVSS voltage signal, and the first power trace 60 may have a large widthto reduce a resistance of the first power trace 60, so as to reduce avoltage drop generated during a transmission of the VSS voltage signalon the first power trace 60. In the embodiments of the presentdisclosure, the first power trace 60 with the large width is stackedwith the scan driving circuit. In this way, the first power trace 60with the large width may be avoided to be arranged side by side with thescan driving circuit. Therefore, the stacked-layer design may greatlyreduce the occupation width of the first power trace in the peripheralarea, so that the width of the frame of the display substrate may bereduced.

As described above, the first scan driving circuit 20 may include aplurality of gate scanning shift register units 201 connected in cascadefor providing the plurality of pixel units P with, for example, gatescanning signals shifted row by row.

FIG. 6 shows a circuit diagram of a gate scanning shift register unit201 included in the first scan driving circuit 20 according to someexemplary embodiments of the present disclosure. FIG. 7 shows aschematic diagram of a layout of the gate scanning shift register unit201 included in the first scan driving circuit 20 on the base substrateaccording to some exemplary embodiments of the present disclosure.

Referring to FIG. 6 and FIG. 7, the gate scanning shift register unit201 may include eight transistors (an input transistor T21, a firstcontrol transistor T22, a second control transistor T23, an outputcontrol transistor T24, a gate output transistor T25, a first noisereduction transistor T26, a second noise reduction transistor T27, and avoltage stabilization transistor T28) and two capacitors (a firstscanning capacitor C21 and a second scanning capacitor C22). Forexample, when the plurality of gate scanning shift register units 201are connected in cascade, a first electrode of the input transistor T21in a first stage of gate scanning shift register unit 201 is connectedto an input terminal IN, and the input terminal IN is connected to atrigger signal line GSTV so as to receive a trigger signal as an inputsignal. The first electrode of the input transistor T21 in other stageof gate scanning shift register unit 201 is connected to the outputterminal of a previous stage of gate scanning shift register unit 201,so as receive an output signal output by an output terminal GOUT of theprevious stage of gate scanning shift register unit 201 as an inputsignal. In this way, a shift output may be achieved to scan the array ofpixel units located in the display area row by row.

For example, the input transistor T21 has a gate electrode connected toa first sub-clock signal line GCK, a second electrode connected to theinput terminal IN, and a first electrode connected to a first scan nodeN21. The first control transistor T22 has a gate electrode connected toa first scan node N21, a second electrode connected to the firstsub-clock signal line GCK, and a first electrode connected to a secondscan node N22. The second control transistor T23 has a gate electrodeconnected to the first sub-clock signal line GCK, a second electrodeconnected to a second power line VGL, and a first electrode connected tothe second scan node N22. The output control transistor T24 has a gateelectrode connected to the second scan node N22, a first electrodeconnected to a third power line VGH, and a second electrode connected tothe output terminal GOUT. The first scanning capacitor C21 has a firstelectrode connected to the second scan node N22, and a second electrodeconnected to the third power line VGH. The gate output transistor T25has a gate electrode connected to the third scan node N23, a firstelectrode connected to a second sub-clock signal line GCB, and a secondelectrode connected to the output terminal GOUT. The second scanningcapacitor C22 has a first electrode connected to a third scan node N23,and a second electrode connected to the output terminal GOUT. The firstnoise reduction transistor T26 has a gate electrode connected to thesecond scan node N22, a first electrode connected to the third powerline VGH, and a second electrode connected to a second electrode of thesecond noise reduction transistor T27. The second noise reductiontransistor T27 has a gate electrode connected to the second sub-clocksignal line GCB, and a first electrode connected to the first scan nodeN21. The voltage stabilization transistor T28 has a gate electrodeconnected to the second power line VGL, a second electrode connected tothe first scan node N21, and a first electrode connected to the thirdscan node N23.

A P-type transistor is illustrated by way of example in describing thetransistors in the gate scanning shift register unit 201 shown in FIG.6. That is, each transistor is turned on when the gate electrode isconnected to a low level (a turn-on level), and is turned off when thegate electrode is connected to a high level (a turn-off level). In thiscase, the first electrode of the transistor may be the source electrode,and the second electrode of the transistor may be the drain electrode.

It should be noted that, in the embodiments of the present disclosure,the gate scanning shift register unit includes but is not limited to theconfiguration shown in FIG. 6 and FIG. 7. For example, the capacitor C22in the gate scanning shift register unit 201 may be connected betweenthe second scan node N22 and the second sub-clock signal line GCB, andthe node N22 may be provided with a transistor, such as the voltagestabilization transistor T28, and other transistor with a similarfunction. The various transistors may also be N-type transistors, or amixture of P-type transistor and N-type transistor may be adopted, aslong as a port polarity of the selected type of transistor is connectedaccording to the port polarity of the corresponding transistor in theembodiments of the present disclosure.

It should be noted that an operation principle of the gate scanningshift register unit may refer to an introduction in the art, which willnot be repeated here.

For example, a gate scanning signal output by the gate scan drivingcircuit is maintained at an active level (for example, a low level) fora short time period of a frame so as to output to the pixel circuit.That is, the gate scan driving circuit may output an effective signalduring a time period when the data signal should be written in the pixelin a frame. The light emission control signal output by the EM GOA maybe maintained at an active level (for example, a low level) for a longtime period in a frame so as to output to the pixel circuit, so that thepixel may be controlled to emit light in a long time period in theframe.

As described above, the second scan driving circuit 30 may include aplurality of light emission control scanning shift register units 301connected in cascade for providing the plurality of pixel units P with,for example, light emission control signals shifted row by row.

FIG. 8 shows a circuit diagram of the light emission control scanningshift register unit 301 included in the second scan driving circuit 30according to some exemplary embodiments of the present disclosure. FIG.9 shows a schematic diagram of a layout of the light emission controlscanning shift register unit 301 included in the second scan drivingcircuit 30 on the base substrate according to some exemplary embodimentsof the present disclosure.

As shown in FIG. 8, in some embodiments, at least one shift registerunit of the plurality of shift register units may include tentransistors and three capacitors, for example, including a firstcapacitor C1, an output capacitor C2, an output reset capacitor C3, anoutput transistor T10, an output reset transistor T9, a first transistorT1, a second transistor T2, a third transistor T3, a fourth transistorT4, a fifth transistor T5, a sixth transistor T6, a seventh transistorT7, and an eighth transistor T8.

The output transistor T10 has a gate electrode G10 coupled to a firstplate C2 a of the output capacitor C2, a first electrode S10 coupled tothe second voltage signal line VGL, and a second electrode D10 coupledto a signal output line E0.

The output reset transistor T9 has a gate electrode G9 coupled to afirst plate C3 a of the output reset capacitor C3, a first electrode S9coupled to a second plate C3 b of the output reset capacitor C3, and asecond electrode D9 coupled to the signal output line E0.

The output reset capacitor C3 has the second plate C3 b coupled to thefirst voltage signal line VGH, and the output capacitor C2 has a secondplate C2 b coupled to a second clock signal line CB.

The first transistor T1 has a first electrode S1 coupled to the secondclock signal line CB, a second electrode D1 of the first transistor T1and a first electrode S2 of the second transistor T2 are respectivelycoupled to the second plate C 1 b of the first capacitor C1, and a gateelectrode G1 of the first transistor T1 is coupled to the first plate C1a of the first capacitor C1.

A gate electrode G2 of the second transistor T2 and a gate electrode G7of the seventh transistor T7 are respectively coupled to the first clocksignal line CB, a second electrode D2 of the second transistor T2 iscoupled to a second electrode D3 of the third transistor T3, and thefirst electrode S2 of the second transistor T2 is coupled to the secondplate C 1 b of the first capacitor.

The third transistor T3 has a gate electrode G3 coupled to the gateelectrode G10 of the output transistor T10, and a first electrode S3coupled to the first voltage signal line VGH.

A gate electrode G4 of the fourth transistor T4 and a gate electrode G5of the fifth transistor T5 are both coupled to the first clock signalline CK, a first electrode S4 of the fourth transistor T4 and the firstelectrode S10 of the output transistor T10 are both coupled to thesecond voltage signal line VGL, and a second electrode D4 of the fourthtransistor T4 is coupled to a second electrode D6 of the sixthtransistor T6.

The fifth transistor T5 has the gate electrode G5 coupled to the firstclock signal line CK, a second electrode D5 coupled to a gate electrodeG6 of the sixth transistor T6, and a first electrode S5 coupled to aninput signal terminal E1.

A first electrode S6 of the sixth transistor T6 and the gate electrodeG4 of the fourth transistor T4 are both coupled to the first clocksignal line CK, the second electrode D6 of the sixth transistor T6 iscoupled to the second electrode D4 of the fourth transistor T4, and thegate electrode G6 of the sixth transistor T6 is coupled to the secondelectrode D5 of the fifth transistor T5.

The gate electrode G7 of the seventh transistor T7 and the second plateC2 b of the output capacitor C2 are both coupled to the second clocksignal line CB, a first electrode S7 of the seventh transistor T7 iscoupled to a second electrode D8 of the eighth transistor T8, and asecond electrode D7 of the seventh transistor T7 is coupled to the gateelectrode G6 of the sixth transistor T6.

The eighth transistor T8 has a gate electrode G8 coupled to the gateelectrode G1 of the first transistor T1, and a first electrode S8coupled to the first voltage signal line VGH.

A P-type transistor is illustrated by way of example in describing thetransistors in the light emission control scanning shift register unit301 shown in FIG. 8. That is, each transistor is turned on when the gateelectrode is connected to a low level (a turn-on level), and is turnedoff when the gate electrode is connected to a high level (a turn-offlevel). In this case, the first electrode of the transistor may be thesource electrode, and the second electrode of the transistor may be thedrain electrode.

It should be noted that, in the embodiments of the present disclosure,the light emission control scanning shift register unit includes but isnot limited to the configuration shown in FIG. 8 and FIG. 9.

In FIG. 8, the first node is denoted by N1, the second node is denotedby N2, the third node is denoted by N3, and the fourth node is denotedby N4.

In the embodiments shown in FIG. 8 and FIG. 9, the first voltage signalline VGH may provide a high voltage Vgh, and the second voltage signalline VGL may provide a low voltage Vgl, but it is not limited to this.

As shown in FIG. 9, the shift register unit may include a firstcapacitor C1, an output capacitor C2, an output reset capacitor C3, anoutput transistor T10, an output reset transistor T9, a first transistorT1, a second transistor T2, a third transistor T3, a fourth transistorT4, a fifth transistor T5, a sixth transistor T6, a seventh transistorT7, and an eighth transistor T8.

The output transistor T10 and the output reset transistor T9 may bearranged in second direction Y. The output capacitor C2 is arranged on aside of the output transistor T10 away from the second voltage signalline VGL, and the transistors T5, T6 and T4 are arranged between theoutput capacitor C2 and the first voltage signal line VGH.

The transistors T1 and T3 are arranged on a side of the output resettransistor T9 away from the second voltage signal line VGL, the firstcapacitor C1 is arranged on a side of the third transistor T3 away fromthe output reset transistor T9, and the eighth transistor T8 and thesecond transistor T2 are arranged on a side of the first capacitor C1away from the eighth transistor T8.

The transistors T5, T7, T8, T2 and the output reset capacitor C3 arearranged in sequence in the second direction Y, the sixth transistor T6and the capacitors C1 and C3 are arranged in sequence in the seconddirection Y, and the output capacitor C2, the first transistor Ti, thethird transistor T3 and the output reset capacitor C3 are arranged insequence in the second direction Y.

In FIG. 9, a first output line portion of the signal output line isdenoted by E01, a first second output line portion of the signal outputline is denoted by E021, and a second second output line portion of thesignal output line is denoted by E022. E01 extends in the seconddirection Y, E021 extends in the first direction X, and the output lineportions E01, E021 and E022 are coupled to each other. The firstdirection X intersects the second direction Y. E01 is arranged betweenthe second voltage signal line VGL and the output circuit (the outputcircuit includes the output transistor T10 and the output resettransistor T9), and the output line portions E021 and E022 extend towardthe display area AA in the first direction X, so as to provide the lightemission control signal to the pixel driving circuit located in thedisplay area.

In FIG. 8 and FIG. 9, G1 represents the gate electrode of Ti, S1represents the first electrode of Ti, and D1 represents the secondelectrode of Ti; G2 represents the gate electrode of T2, S2 representsthe first electrode of T2, and D2 represents the second electrode of T2;G3 represents the gate electrode of T3, S3 represents the firstelectrode of T3, and D3 represents the second electrode of T3; G4represents the gate electrode of T4, S4 represents the first electrodeof T4, and D4 represents the second electrode of T4; G5 represents thegate electrode of T5, S5 represents the first electrode of T5, and D5represents the second electrode of T5; G6 represents the gate electrodeof T6, S6 represents the first electrode of T6, and D6 represents thesecond electrode of T6; G7 represents the gate electrode of T7, S7represents the first electrode of T7, and D7 represents the secondelectrode of T7; G8 represents the gate electrode of T8, and S8represents the first electrode of T8; G9 represents the gate electrodeof T9, S9 represents the first electrode of T9, and D9 represents thesecond electrode of T9; G10 represents the gate electrode of T10, S10represents the first electrode of T10, and D10 represents the secondelectrode of T10.

In the embodiment shown in FIG. 9, the first direction X may be ahorizontal direction from right to left, and the second direction Y maybe a vertical direction from top to bottom, but the embodiment of thepresent disclosure is not limited thereto. In practical operation, thefirst direction may also be a vertical direction from bottom to top, andthe second direction may also be a horizontal direction from left toright. Alternatively, the first direction may also be other directions,and the second direction may also be other directions.

It should be noted that the shift register unit shown in FIG. 7 and FIG.9 may be an n-th stage of shift register unit included in the scandriving circuit, where n is a positive integer.

In the embodiments of the present disclosure, an orthographic projectionof a circuit on the base substrate may be represented by an occupationarea of the circuit. The expression “occupation area of the circuit”refers to a largest area covered by an orthographic projection ofvarious components (such as a plurality of transistors and a pluralityof capacitors) included in the circuit on the base substrate. Forexample, the orthographic projection of the various components includedin the circuit on the base substrate has two sides farthest apart in thefirst direction X and two sides farthest apart in the second directionY. Extension lines of these four sides may cross to surround and form anarea, which is the occupation area of the circuit.

Specifically, referring to FIG. 7, a schematic diagram of a layout ofthe shift register unit 201 included in the first scan driving circuit20 on the display substrate is schematically shown. As described above,the shift register unit 201 may include eight transistors (an inputtransistor T21, a first control transistor T22, a second controltransistor T23, an output control transistor T24, a gate outputtransistor T25, a first noise reduction transistor T26, a second noisereduction transistor T27, and a voltage stabilization transistor T28)and two capacitors (a first scanning capacitor C21 and a second scanningcapacitor C22). Accordingly, the occupation area of a shift registerunit 201 may be indicated by a largest area covered by an orthographicprojection of a combination of the eight transistors and the twocapacitors on the base substrate. As shown in FIG. 7, a dashed box isused to schematically show the occupation area of the shift registerunit 201 included in the first scan driving circuit 20. The occupationarea has a size in the first direction X (that is, a width W1) and asize in the second direction Y (that is, a length L1), and theoccupation area has a rectangular shape. The first scan driving circuit20 includes n shift register units 201. Accordingly, the orthographicprojection of the first scan driving circuit 20 on the base substrate 10may be represented by an occupation area formed by a combination of ndashed boxes as shown in FIG. 7.

Referring to FIG. 9, a schematic diagram of a layout of the shiftregister unit 301 included in the second scan driving circuit 30 on thedisplay substrate is schematically shown. As described above, the shiftregister unit 301 may include ten transistors (an output transistor T10,an output reset transistor T9, a first transistor T1, a secondtransistor T2, a third transistor T3, a fourth transistor T4, a fifthtransistor T5, a sixth transistor T6, a seventh transistor T7, and aneighth transistor T8) and three capacitors (a first capacitor C1, anoutput capacitor C2, and an output reset capacitor C3). Accordingly, theoccupation area of the shift register unit 301 may be represented by alargest area covered by an orthographic projection of a combination ofthe ten transistors and the three capacitors on the base substrate. Asshown in FIG. 9, a dashed box is used to schematically show theoccupation area of the shift register unit 301 included in the secondscan driving circuit 30. The occupation area has a size in the firstdirection X (that is, a width W2) and a size in the second direction Y(that is, a length L2), and the occupation area has a rectangular shape.The second scan driving circuit 30 includes n shift register units 301.Accordingly, the orthographic projection of the second scan drivingcircuit 30 on the base substrate 10 may be represented by an occupationarea formed by a combination of n dashed boxes as shown in FIG. 9.

Exemplarily, referring to FIG. 1 to FIG. 9 in combination, in theperipheral area NA, the active layer of each transistor of the scandriving circuit may be located in the semiconductor layer 2, the gateelectrode of each transistor of the scan driving circuit may be locatedin the first conductive layer 4, and the first electrode and the secondelectrode of each transistor of the scan driving circuit may be locatedin the second conductive layer 5. That is, the active layer, the gateelectrode and the source/drain electrode of each transistor of the scandriving circuit located in the peripheral area NA are respectivelylocated in the same layer as the active layer, the gate electrode andthe source/drain electrode of each transistor of the pixel drivingcircuit located in the display area AA.

In the embodiments of the present disclosure, the first power trace 60is located in the third conductive layer 6, that is, the layer where thefirst power trace 60 is located is located on a side of the layer wherethe scan driving circuit is located away from the base substrate 10.That is, the first power trace 60 and the scan driving circuit arelocated in different layers, which may facilitate the realization of thestacked-layer design of the first power trace 60 and the scan drivingcircuit.

For example, in the peripheral area NA, a part of the third insulatinglayer 33 is arranged between the first power trace 60 and the scandriving circuit.

In some embodiments of the present disclosure, referring to FIG. 1 andFIG. 3, the second scan driving circuit 30 is located on a side of thefirst scan driving circuit 20 away from the display area AA. That is, anorthographic projection of the second scan driving circuit 30 on thebase substrate 10 is located on a side of the orthographic projection ofthe first scan driving circuit 20 on the base substrate 10 away from thedisplay area AA.

Exemplarily, the orthographic projection of the first power trace 60 onthe base substrate 10 may cover the orthographic projection of thesecond scan driving circuit 30 on the base substrate 10. For example,the orthographic projection of the first power trace 60 on the basesubstrate 10 may completely cover the orthographic projection of thesecond scan driving circuit 30 on the base substrate 10.

Exemplarily, the orthographic projection of the first power trace 60 onthe base substrate 10 may partially overlap the orthographic projectionof the first scan driving circuit 20 on the base substrate 10. Forexample, a width W3 of an overlapping portion of the orthographicprojection of the first power trace 60 and the orthographic projectionof the first scan driving circuit 20 in the first direction X is morethan 40% of a width W60 of the first power trace 60 in the firstdirection X. The first direction X is a direction from the display areaAA to the peripheral area NA. For example, the width W3 of theoverlapping portion of the orthographic projection of the first powertrace 60 and the orthographic projection of the first scan drivingcircuit 20 in the first direction X is more than 50% of the width W60 ofthe first power trace 60 in the first direction X.

Exemplarily, referring to FIG. 3, the first scan driving circuit 20 isspaced apart from the second scan driving circuit 30, and theorthographic projection of the first power trace 60 on the basesubstrate 10 covers an orthographic projection of a gap 202 between thefirst scan driving circuit 20 and the second scan driving circuit 30 onthe base substrate 10.

Exemplarily, referring to FIG. 4, the first scan driving circuit 20 isspaced apart from the second scan driving circuit 30. The first powertrace 60 includes a first sub-trace 60A and a second sub-trace 60B, andthe first sub-trace 60A is spaced apart from the second sub-trace 60B. Agap 60C between the first sub-trace 60A and the second sub-trace 60B mayexpose the gap 202 between the first scan driving circuit 20 and thesecond scan driving circuit 30. That is, an orthographic projection ofthe gap 60C between the first sub-trace 60A and the second sub-trace 60Bon the base substrate 10 may cover an orthographic projection of the gap202 between the first scan driving circuit 20 and the second scandriving circuit 30 on the base substrate 10.

Referring to FIG. 3 and FIG. 4, the display substrate 1 further includesa conductive connecting portion 70. The conductive connecting portion 70is located between the layer where the first power trace 60 is locatedand the layer where the first electrode 501 is located, so as toelectrically connect the first power trace 60 and the first electrode501. For example, the conductive connecting portion 70 may be located inthe fourth conductive layer 7. That is, the conductive connectingportion 70 and the second electrode 502 are located in the same layerand are made of the same material.

Exemplarily, an orthographic projection of the conductive connectingportion 70 on the base substrate 10 may at least partially overlap theorthographic projection of the first scan driving circuit 20 on the basesubstrate 10, and the orthographic projection of the conductiveconnecting portion 70 on the base substrate 10 may cover theorthographic projection of the second scan driving circuit 30 on thebase substrate 10.

Exemplarily, the conductive connecting portion 70 is in contact with thefirst power trace 60, and a width of a portion of the first power trace60 in contact with the conductive connecting portion 70 in the firstdirection X is more than 50% of the width W60 of the first power trace60 in the first direction X. For example, referring to FIG. 3, theorthographic projection of the conductive connecting portion 70 on thebase substrate 10 substantially covers the orthographic projection ofthe first power trace 60 on the base substrate 10. In this embodiment,the width of the portion of the first power trace 60 in contact with theconductive connecting portion 70 in the first direction X is more than80% of the width of the first power trace 60 in the first direction X.In the embodiments of the present disclosure, a contact portion betweenthe first power trace 60 and the conductive connecting portion forelectrically connecting the first power trace 60 and the first electrode501 has a large width, which is beneficial to reduce a contactresistance, so as to facilitate an electrical connection between thefirst power trace 60 and the first electrode 501.

For example, the orthographic projection of the conductive connectingportion 70 on the base substrate 10 may at least partially overlap theorthographic projection of the first power trace 60 on the basesubstrate 10. For example, a width of the orthographic projection of theconductive connecting portion 70 on the base substrate 10 in the firstdirection X may be substantially equal to or greater than the width W60of the orthographic projection of the first power trace 60 on the basesubstrate 10 in the first direction X. The conductive connecting portion70 has a first side edge 70S away from the display area AA, and thefirst power trace 60 has a first side edge 60S away from the displayarea AA. The first side edge 70S of the conductive connecting portion 70and the first side edge 60S of the first power trace 60 aresubstantially aligned in the thickness direction of the displaysubstrate. That is, an orthographic projection of the first side edge70S of the conductive connecting portion 70 on the base substrate 10substantially coincides an orthographic projection of the first sideedge 60S of the first power trace 60 on the base substrate 10. Throughthis arrangement, a large contact area between the conductive connectingportion 70 and the first power trace 60 may be ensured, which isbeneficial to reduce the contact resistance, so as to facilitate theelectrical connection between the first power trace 60 and the firstelectrode 501.

In some exemplary embodiments of the present disclosure, the displaysubstrate 1 may further include an auxiliary trace 90 located in theperipheral area NA. The auxiliary trace 90 is located on a side of thesecond scan driving circuit 30 away from the display area AA and islocated on a side of the first power trace 60 close to the basesubstrate 10, and the auxiliary trace 90 is electrically connected tothe first power trace 60. For example, the auxiliary trace 90 may belocated in at least one of the first conductive layer 4 and the secondconductive layer 5. The first power trace 60 is electrically connectedto the auxiliary trace 90 through a via hole or a groove. In this way, asignal such as a VSS voltage may be transmitted through parallel traceslocated in different conductive layers, which may further reduce aninfluence of the voltage drop on the transmitted signal.

In some exemplary embodiments of the present disclosure, the displaysubstrate 1 may further include a first barrier component 81 arranged ona side of the first power trace 60 away from the base substrate 10, andan orthographic projection of the first barrier component 81 on the basesubstrate 10 at least partially overlaps the orthographic projection ofthe second scan driving circuit 30 on the base substrate 10.

For example, the second scan driving circuit 30 may include an edgeportion 302 away from the display area AA, and the orthographicprojection of the first barrier component 81 on the base substrate 10 islocated on a side of an orthographic projection of the edge portion 302on the base substrate 10 close to the display area AA.

In some exemplary embodiments of the present disclosure, the displaysubstrate 1 may further include a second barrier component 82 arrangedon a side of the first power trace 60 away from the base substrate 10,and the second barrier component 82 is located on a side of the firstbarrier component 81 away from the display area AA.

For example, referring to FIG. 4, an orthographic projection of thesecond barrier component 82 on the base substrate 10 at least partiallyoverlaps an orthographic projection of the edge portion 302 of thesecond scan driving circuit 30 on the base substrate 10.

Referring to FIG. 3 and FIG. 4, the first barrier component 81 is spacedapart from the second barrier component 82. At least a part of the firstbarrier component 81 may be located in the same layer as the pixeldefining layer PDL, and at least a part of the second barrier component82 may be located in the same layer as the pixel defining layer PDL.

Exemplarily, the display substrate 1 may further include anencapsulation layer TFE arranged on a side of the first barriercomponent 81 and the second barrier component 82 away from the basesubstrate 10. For example, the encapsulation layer TFE may include afirst encapsulation sub-layer TFE1, a second encapsulation sub-layerTFE2 and a third encapsulation sub-layer TFE3 that are sequentiallyarranged in a direction away from the base substrate 10. For example,the first encapsulation sub-layer TFE1 and the third encapsulationsub-layer TFE3 may be formed of an inorganic material, and the secondencapsulation sub-layer TFE2 may be formed of an organic material.

For example, the first barrier component 81 and the second barriercomponent 82 may block the organic material from flowing to the outsideof the barrier component during a process of forming the secondencapsulation sub-layer TFE2. Thus, in the embodiments of the presentdisclosure, a boundary of the second encapsulation sub-layer TFE2 awayfrom the display area AA is located within the first barrier component81, or a boundary of the second encapsulation sub-layer TFE2 away fromthe display area AA is located within the second barrier component 82.Here, the expression “outside” refers to a side away from the displayarea AA in the first direction X, and the expression “inside” refers toa side close to the display area AA in the first direction X. Inaddition, the first barrier component 81 and the second barriercomponent 82 may further prevent water vapor and oxygen from entering aninterior of the display substrate, and may reduce a possibility of acrack formed during cutting and opening extending into the displaysubstrate, so as to improve a package reliability.

FIG. 10 shows a schematic diagram of a display device according to someexemplary embodiments of the present disclosure. The display device 100includes the display substrate described above. For example, it includesthe display area AA and the peripheral area NA. The film layer structurein the display area AA and the peripheral area NA may refer to thedescription of various embodiments described above, which will not berepeated here.

The display device may include any apparatus or product with a displayfunction. For example, the display device may be a smart phone, a mobilephone, an e-book reader, a personal computer (PC), a laptop PC, anetbook PC, a personal digital assistant (PDA), a portable multimediaplayer (PMP), a digital audio player, a mobile medical apparatus, acamera, a wearable device (such as a head-mounted device, electronicclothing, electronic bracelet, electronic necklace, electronicaccessory, electronic tattoo or smart watch), a television, and so on.

It should be understood that the display device according to theembodiments of the present disclosure may have all the features andadvantages of the display substrate described above. The details mayrefer to the above description.

Although some embodiments of the general technical concept of thepresent disclosure have been illustrated and described, it should beunderstood by those of ordinary skilled in the art that theseembodiments may be changed without departing from the principle andspirit of the general technical concept of the present disclosure. Thescope of the present disclosure is defined by the claims and theirequivalents.

What is claimed is:
 1. A display substrate, comprising: a base substratecomprising a display area and a peripheral area located at least on afirst side of the display area; a plurality of pixel units arranged inthe display area of the base substrate, wherein the pixel units comprisea pixel driving circuit and a light emitting device electricallyconnected to the pixel driving circuit, and the light emitting devicecomprises a first electrode; a first power trace located in theperipheral area and electrically connected to the first electrode; and ascan driving circuit arranged on the base substrate and located in theperipheral area, wherein the scan driving circuit comprises a first scandriving circuit for generating a first scan signal and a second scandriving circuit for generating a second scan signal, wherein a layerwhere the first power trace is located is located on a side of a layerwhere the scan driving circuit is located away from the base substrate;and wherein an orthographic projection of the first power trace on thebase substrate at least partially overlaps an orthographic projection ofthe first scan driving circuit on the base substrate, and theorthographic projection of the first power trace on the base substrateat least partially overlaps an orthographic projection of the secondscan driving circuit on the base substrate.
 2. The display substrate ofclaim 1, wherein the second scan driving circuit is located on a side ofthe first scan driving circuit away from the display area, and theorthographic projection of the first power trace on the base substratecovers the orthographic projection of the second scan driving circuit onthe base substrate.
 3. The display substrate of claim 2, wherein a widthof an overlapping portion of the orthographic projection of the firstpower trace on the base substrate and the orthographic projection of thefirst scan driving circuit on the base substrate in a first direction ismore than 40% of a width of the first scan driving circuit in the firstdirection, wherein the first direction is a direction from the displayarea to the peripheral area.
 4. The display substrate of claim 1,wherein the first scan driving circuit is spaced apart from the secondscan driving circuit, and the orthographic projection of the first powertrace on the base substrate covers an orthographic projection of a gapbetween the first scan driving circuit and the second scan drivingcircuit on the base substrate.
 5. The display substrate of claim 1,wherein: the first scan driving circuit is spaced apart from the secondscan driving circuit; the first power trace comprises a first sub-traceand a second sub-trace, and the first sub-trace is spaced apart from thesecond sub-trace; and a gap between the first sub-trace and the secondsub-trace exposes a gap between the first scan driving circuit and thesecond scan driving circuit.
 6. The display substrate of claim 1,further comprising a conductive connecting portion located at leastpartially between the layer where the first power trace is located and alayer where the first electrode is located, so as to electricallyconnect the first power trace and the first electrode.
 7. The displaysubstrate of claim 6, wherein an orthographic projection of theconductive connecting portion on the base substrate at least partiallyoverlaps the orthographic projection of the first scan driving circuiton the base substrate, and the orthographic projection of the conductiveconnecting portion on the base substrate covers the orthographicprojection of the second scan driving circuit on the base substrate. 8.The display substrate of claim 7, wherein the conductive connectingportion is in contact with the first power trace, and a width of aportion of the first power trace in contact with the conductiveconnecting portion in the first direction is more than 50% of a width ofthe first power trace in the first direction, wherein the firstdirection is a direction from the display area to the peripheral area.9. The display substrate of claim 1, further comprising a first barriercomponent arranged on a side of the first power trace away from the basesubstrate, wherein an orthographic projection of the first barriercomponent on the base substrate at least partially overlaps theorthographic projection of the second scan driving circuit on the basesubstrate.
 10. The display substrate of claim 9, wherein the second scandriving circuit comprises an edge portion away from the display area,and the orthographic projection of the first barrier component on thebase substrate is located on a side of an orthographic projection of theedge portion on the base substrate close to the display area.
 11. Thedisplay substrate of claim 9, further comprising a second barriercomponent arranged on a side of the first power trace away from the basesubstrate, wherein the second barrier component is located on a side ofthe first barrier component away from the display area; and wherein anorthographic projection of the second barrier component on the basesubstrate at least partially overlaps an orthographic projection of theedge portion of the second scan driving circuit on the base substrate.12. The display substrate of claim 1, further comprising a conductivetrace located in the peripheral area, wherein the conductive trace islocated on a side of the second scan driving circuit away from thedisplay area and is located on a side of the first power trace close tothe base substrate, and the conductive trace is electrically connectedto the first power trace.
 13. The display substrate of claim 1, whereinthe light emitting device further comprises a second electrode and alight emitting layer arranged between the first electrode and the secondelectrode, the scan driving circuit comprises at least one thin filmtransistor arranged on the base substrate, and the thin film transistorcomprises an active layer, a gate electrode, a source electrode and adrain electrode; and wherein the display substrate further comprises: afirst conductive layer arranged on a side of the active layer away fromthe base substrate, wherein the gate electrode is located in the firstconductive layer; a second conductive layer arranged on a side of thefirst conductive layer away from the base substrate, wherein the sourceelectrode and the drain electrode are located in the second conductivelayer; and a third conductive layer arranged on a side of the secondconductive layer away from the base substrate, wherein at least aportion of the second power trace is located in the second conductivelayer and/or the third conductive layer.
 14. The display substrate ofclaim 1, wherein the first electrode is a cathode electrode of anorganic light emitting device, and the second electrode is an anodeelectrode of the organic light emitting device.
 15. A display devicecomprising the display substrate of claim 1.